Wafer-Level Chip Scale Packages: Reliability and Validation Testing Using Simulation Methodology
October 8, 2018
SEMI spoke with Balaji Nandhivaram Muthuraman, Package and Material Simulation engineer at Dialog Semiconductor, about the state of reliability testing for wafer-level chip scale packages ahead of his presentation at the Advanced Packaging Conference
3D Heterogeneous Integration Drives Demand for New Materials and Integration Solutions
October 2, 2018
SEMI met with Gerald Beyer, program manager at imec, to discuss the co-existence of various 3D interconnect technologies and their need for new materials and integration solutions. The two talked in the runup to his presentation at the Advanced...